A conventional structure for forming a stack capacitor in a 16 MB DRAM is a rugged polysilicon layer having a thickness of about 850 .ANG.. Usually, the rugged polysilicon is formed on an upper surface of the other polysilicon layer having contact holes, and the wall of the contact holes, by a low pressure chemical vapor deposition (LPCVD). The stack capacitor will be constructed on the surface of the rugged polysilicon layer.
To reduce costs, the radius of a wafer is reduced and the number of integrated circuits on a wafer is increased in a semiconductor manufacture process. Unfortunately, when the wire size in a semiconductor manufacture process is reduced from 0.45 .mu.m to 0.38 .mu.m or less, a serious problem for the conventional technique of forming the stack capacitor on the DRAM will occur. That is, to maintain the capacitance of the stack capacitor structure, the thickness of the rugged polysilicon layer must be increased to enlarge the surface area of the stack capacitor structure. However, the added rugged polysilicon will fill up the contact hole and therefore reduce the overall surface of the rugged polysilicon layer instead of increasing it. In other words, the capacitance of the stack capacitor is insufficient in a 0.38 .mu.m or less wire size semiconductor manufacture process on which the conventional technique of forming the rugged polysilicon layer is applied.
For the above reason, it is desirable to invent a process and a structure for a 0.38 .mu.m or less wire size semiconductor manufacture process to maintain the capacitance of the stack capacitor of a DRAM. It is then attempted by the applicant to design such a process and such a structure.